The present invention relates to a clock synchronizing circuit capable of obtaining a plurality of outputs in one clock signal, and to a method of designing the clock synchronizing circuit.
Digital circuits integrated by LSI (large scale integration) are usually clock synchronizing type circuit structures in which a combinatorial logic circuit is divided at sequential circuits, such as flip-flop circuits or latch circuits or the like. The structure of a conventional clock synchronizing circuit is shown in FIG. 9. Reference numerals 101 through 106 respectively represent rising edge trigger flip-flop circuits, and reference numeral 107 represents an arbitrary combinatorial logic circuit. FIG. 10 is a timing chart showing operations of the clock synchronizing circuit. As shown in FIG. 10, at the rising edges (T0, T2) of the clock signal, the flip-flop circuit samples the value of the input data (for example, signal 109), and outputs the sampled value. Thus, the output of the flip-flop circuit can produce a single output data for one clock cycle.
In such a clock synchronizing circuit, the clock tree, which is formed by the buffer and the sequential circuits, accounts for a large amount of the electric power which is consumed. A gated clock method is a general method for reducing the amount of power consumed by the clock tree. In this method, the circuit is divided into a plurality of blocks, and the supply of the clock signal is temporarily stopped for circuit blocks which do not need to be operated.
However, in the gated clock method, clock signals must be supplied to circuit blocks which need to be operated, and thus, there are limits to reducing the amount of power which is consumed.
It is an object of the present invention is to provide a clock synchronizing circuit in which the amount of consumed power can always be reduced regardless of the operational state, and to a method of designing the clock synchronizing circuit.
The clock synchronizing circuit according to one aspect of the present invention comprises a plurality of sequential circuits which operate on the basis of a single clock signal. Each of the sequential circuits carries out sampling of input data and changing of output data at both a rising edge and a falling edge of the clock signal. Moreover, each of the sequential circuits includes an input selector unit which receives two inputs and selects any one of the two inputs in accordance with a predetermined control signal. An output of a desired one of the sequential circuit is input as one input of the input selector unit provided in another sequential circuit which is provided at a subsequent stage to the desired sequential circuit thereby forming a series of scan pass in sequential circuits.
The clock synchronizing circuit according to another aspect of the present invention comprises a plurality of sequential circuits which operate on the basis of a single clock signal. Each of the sequential circuits carries out sampling of input data and changing of output data at both a rising edge and a falling edge of the clock signal. Moreover, each of the sequential circuits includes an input selector unit which receives an input signal and an inverted signal of the input signal and selects and outputs any one of the input signal and the inverted signal in accordance with a predetermined control signal. An output of one sequential circuit is input into the input selector unit provided in the same sequential circuit, and the output of the one sequential circuit is input into a clock terminal of a sequential circuit provided at a subsequent stage to the desired sequential circuit.
According to still another aspect of the present invention, the clock synchronizing circuit of the invention can be generated by the logic synthesis method.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.